FAQ : Design Rules

Q: How does Stone Pillar Suite speed design rule creation and run set generation?

A: Stone Pillar Suite includes capabilities for automatically creating design rules based on unit process capabilities. Design rules are created based on device constructs which are input by the user and which for the basis for a complete model of interlayer interactions. These provide the user with a maximal set of possible design rules from which they can select a subset. The selected subset are then presented for constraint input and based on the input constraints, a set of rues is created. The rules can be filtered and sorted for easy analysis and they form the basis for automatic creation of documentation and run set creation for a number of commercially available DRC tools. The resulting rules can also be imported into the parameterized layout and automatically update complete test chips to reflect rule changes with the click of a button.

Q: Can Stone Pillar SuiteTM help me with my Layout Design Rule optimization process?

A: Stone Pillar Suite provides capabilities tailored to Layout Design Rule optimization. As Design rules have a direct impact upon yield and hence revenue, we have placed the utmost importance on this specific focus area. By generating a parametric model of your design rules, and the related subsequent test structures, Stone Pillar Suite is able to both analyze and optimize Layout Design Rules, with an integrated and highly automated documentation model as a built in capability. Design rules are generated based on unit process alignment and CD control capability, and secondarily are captured in an array of parameterized test structures.

Q: Can Stone Pillar Suite help me with my Electrical Design Rule optimization process?

A: The issue of optimum electrical design rules involves, not only process and device engineering, but is also circuit design dependent. Silicon Insight integrates a statistical simulation framework, along side a parallel, 'real world' data model. This makes it easy to analyze variations in design rules and how they impact both device performance and device failure.



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