FAQ : Test Chips

Q: Can Stone Pillar SuiteTM help me generate and manage test chips?

A: Stone Pillar Suite offers a unique test chip creation capability based on a library of parameterized test device structures or powerful user definable parameterized devices. A large array of test structures may be automatically generated from the parameterized elements. These can be automatically created, placed within a user-defined pad array, and automatically routed. The resulting test chip can be automatically documented. Test chips can be automatically updated to reflect changes in design rules or shifting focus of geometric variations. This makes changes to test structures to reflect global design rule changes a matter of a few mouse clicks.

Q: I already parameterize test chips using a commercial scripting language. Why should I change?

A: Stone Pillar Suite is designed to use parameterized test structures for a variety of reasons, not only to produce a scalable test structure for use with scalable models, in a CAD environment, but also as a basis for automating the generation of wafer level electrical test routines and the analysis and generation of Layout Design Rules. Importantly, during data analysis, these same test structure parameters are used as a basis for device performance and design rule optimization. Typical parameterized test chip methodologies are focused in the area of delivering scalable SPICE models. By contrast, Stone Pillar Suite is largely directed towards the analysis of test structures leading to design rule decisions. By parameterizing test structures designed to analyze design rules, subsequent analysis and Layout Design Rule documentation management becomes far more efficient.

Q: I have generated quite a few test structures with a parameterized scripting language to enable me to deliver scalable devices to the CAD environment. This is water under the bridge; why would I change now?

A: Stone Pillar Suite can read and write to other commercial scripting languages. If an existing parameterized cell is read into Silicon Insight, it may need to be supplemented with additional information. This information is necessary as Stone Pillar Suite provides a lot more value that only a parametric cell. Other capabilities include Layout Design Rule generation, ETest routine generation and automatic documentation. In this sense, your existing parametric cells contain a subset of the required information.

Q: Can Stone Pillar Suite help me to produce parameterized cells faster and with less effort?

A: Existing commercial layout languages available to generate parametric device cells are known to be cumbersome and time consuming to use. Essentially a user has to write each cell from scratch in a script format. Stone Pillar Suite TestChipBuilder is tightly integrated into the rest of the framework, and has been customized to solve the problem of creating test structures and their related infrastructure components, faster. A higher level of automation results in fewer mistakes and faster turn around time. Some of the additional layers of automation include: total tech chip management, modules layout management, pad ring automation, hook up automation, and RF de-embedding structure automation.


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